|Connecting IDE Drives
This text has been published in TCJ several years ago, in
three parts. For your convenience, I concatenated them into
one file again. Sometimes the text refers to other articles
in TCJ, especially to a description of my ECB-bus based
IDE interface. However, I think the information in this text
contains all necessary information about IDE interfacing in
29. October 2001, Tilmann Reh
Remembering the Basics
Let us first have a short look at the drives we want to use.
When discussing the different hard disk interfaces in my
last article, I already pointed out that IDE drives of the
AT-type, thus often called AT-bus drives (Bill Kibler calls
them ATA drives, but this abbreviation is not the usual one,
at least in Europe), are the ones with the best
price/performance ratio one can get. This is even more the
case now. So IDE drives still are the very first choice if
you are looking for a good and cheap hard disk for your
But what's special with those drives? I already mentioned
that the IDE drive contains the complete hard disk
controller. It is accessed with a system-bus interface
compatible with the PC/AT (ISA) bus and offers control and
data registers still compatible with the very first PC/AT
hard disk controller (based on the WD 1010 controller chip).
But even if those specifications come from something I don't
like at all, why not use the low-price components for real
computing (i.e., with a CPU280)?
Bringing the hard disk controller into the drive electronics
offers some advantages. One of the main features is that
you don't have a serial data stream with fixed bit rate
between controller and drive. Thus, there's no need for
conditioning the signals for the interface, and you can use
any bit rate. As a result, the hard disk performance is
limited by the drive technology, not by the interface's bit
rate. This is one reason why today's drives are so much
faster than the older ones. And technologies like Seagate's
ZBR (Zone Bit Recording) are possible with hardware-
There is another main feature of bringing the controller
into the disk drive. Today's drives have very extensive
checks for data security. They store error correction codes
(ECC) together with the sector data and automatically
correct single-bit errors, so the sector need not be re-read
in those cases. Additionally, if a sector is found to be
too unreliable, it is internally marked as bad and the data
is mapped to a spare sector (usually there is one spare
sector per track). All this is absolutely transparent to
the user. So you now know the reason why today's
intelligent drives don't have "defect lists" any more.
Since the PC's have such bad software (and hardware, too),
there is another thing the integrated controller can do:
translate virtual addressing information into physical.
That means that the IDE drive is able to emulate another
drive with different parameters (cylinder count, number of
heads, and sectors per track). For the PC this is necessary
because many PCs don't support drives with other than the
historical 17 sectors per track, and many do not support
free configuration of the drive parameters (only selection
from a table is allowed). Also, some PCs mask off some bits
of the cylinder number, since the first controller only had
a 10-bit cylinder register -- so nearly every IDE drive
still supports an emulation mode with less than 1024
cylinders and 17 sectors per track.
The IDE Interface
As mentioned above, the IDE interface is almost completely
identical with a subset of the PC/AT expansion bus, so the
drive can be connected (almost) directly to that. The only
things required externally are two select signals (I/O
address decoding). This gives us some information about how
the interface works. In a PC the drive is accessed directly
by the CPU via I/O accesses to registers internal to the
drive. The disk data is transferred via the 16-bit data
bus, but for compatibility to the older systems (again!)
only 8 bits are used for command and status information.
Besides the data bus, there are the standard Intel-type data
strobe signals (/IORD and /IOWR), a few address lines, and
some special signals. The connector is a 40-pin header, not
to be confused with the XT-type IDE interface connector,
which is also a 40-pin header but needs somewhat different
hardware and totally different software!
The IDE interface allows connection of two drives with one
cable. The second drive (slave) is then chained to the first
one (master). However, I heard about problems when trying
to connect different drives from different manufacturers.
And the capacities of today's drive are so high that a
single drive will always be enough for an 8-bit personal
computer system! So, I never tried this option.
To understand the interface in detail, let's have a closer
look at the IDE interface connector and its signals:
1 /RES 2 GND
3 D7 4 D8
5 D6 6 D9
7 D5 8 D10
9 D4 10 D11
11 D3 12 D12
13 D2 14 D13
15 D1 16 D14
17 D0 18 D15
19 GND 20 No Pin
21 /IOCHRDY 22 GND
23 /IOWR 24 GND
25 /IORD 26 GND
27 /IOCHRDY 28 ALE
29 No Connection 30 GND
31 IRQ 32 /IO16
33 A1 34 /PDIAG
35 A0 36 A2
37 /CS0 38 /CS1
39 /ACT 40 GND
The signals of the IDE interface can be collected in several
groups: The general control signals are /RES (Reset) and
/PDIAG (Passed Diagnostics). The data bus consists of 16
data lines (D0..D15). The access control lines are three
address lines (A0..A2), the select signals /CS0 and /CS1
(Chip Select 0/1), and the strobe signals /IORD and /IOWR
(and eventually ALE, the address strobe). The remaining
signals (IOCHRDY, IRQ, /ACT, /IO16) are status signals.
Now Let's Go Into Details.
The reset signal normally is active-low. However, I heard
about drives with an active-high reset signal, but I never
saw one (or read such specifications). The /PDIAG pin
carries a bidirectional signal used for chaining two IDE
drives (master/slave). It normally can also be left open.
The data bus carries the 16-bit data words to and from the
host. However, when accessing the control and status
registers of the IDE drives, only data bits 0 through 7 are
used (8-bit transfer). The data bus lines are tri-state
lines that may be connected directly to the host's data bus.
However, to meet the host bus specs and to avoid noise
problems caused by the interface cable, a bus driver IC
should be used to decouple the IDE bus and the host bus.
The drive is accessed using the selection signals /CS0 and
/CS1. This also has historical (compatibility) reasons.
Together with the three address lines, there could be two-
times-eight addresses being occupied by an IDE drive.
However, while the main register set really has eight
registers and is accessed with /CS0 active, the other set
(with /CS1) has only two valid addresses. We will have a
deeper look at all the registers later. The data transfer
is always strobed by the timing signals /IORD and /IOWR, for
reading and writing, respectively. The address strobe (ALE)
is often unused in the drive; it should be pulled high for
static address lines (non-multiplexed busses).
The status signals are not absolutely needed to use IDE
drives. Some of these signals are not commonly delivered at
all (for example, /IOCHRDY (I/O Channel Ready), which is a
WAIT signal for the host when the drive is much slower than
the host processor in terms of interface access times). The
/IO16 line informs the host of 16-bit transfers. Since we
already know that data transfers are always 16-bit and
everything else is always 8-bit, this is redundant (however,
needed in the PC/ATs for their ISA bus). Line /ACT (Active)
is an output which can be used for driving a drive-busy LED.
Line IRQ is an interrupt request line that goes active on
some internal events (if enabled by software).
Most IDE drives contain some jumpers that allow some options
to be selected. This normally includes at least
master/slave selection. Sometimes the /ACT signal may also
be jumpered as an output signalling the presence of a second
(slave) drive. The default state of the jumpers normally
need not be changed (single drive, no special situation).
All interface lines carry CMOS-TTL-compatible signal levels.
However, some signals (IRQ, /PDIAG, /IO16, /ACT) are able to
drive higher currents. Those details should be looked up in
each drive's specifications (for example, the /ACT output
sinks 20 mA on my Conner drive, more than enough for an
Accessing the drive is done with the following sequence of
operations: First, the address lines and the chip selects
must be set according to the desired register address. After
some time (a minimum of 25 ns), /IORD or /IOWR is activated.
This causes the data to appear on the data lines (when
reading) or to be written to the drive (with the trailing
edge of /IOWR, but there are setup and hold times to take
care of). After a minimum of 80 ns, the strobe signal has to
be removed. There are some more timing requirements, but
these are the main ones.
The above timing details might differ from drive to drive.
Always keep in mind that the IDE definition follows the
PC/AT system expansion bus and that official standards were
not specified until two years ago, when the IEEE finally
defined some specifictions (which many PC manufacturers are
Unfortunately, I found that the drives do not match their
own specs in every detail. For example, I found that the
address lines of my Conner drive (a CP-3044 with 42 MB) must
be kept stable for much more than the specified setup time.
In addition, the drive is very sensitive to spike noise on
the address lines, even if the noise appears long before an
access is initiated. I spent a great deal of time
struggling with such unlucky details (fixing other people's
IDE Interface Registers
Now that we've covered the interface signals and their
meaning and usage, let's look at the registers of the
interface. We saw that there are eight addresses being
accessed through /CS0 and two addresses through /CS1. The
following is a list of all the internal registers of an IDE
/CS0 /CS1 A2 A1 A0 Addr. Read Function Write Function
0 1 0 0 0 1F0 Data Register Data Register
0 1 0 0 1 1F1 Error Register (Write Precomp Reg.)
0 1 0 1 0 1F2 Sector Count Sector Count
0 1 0 1 1 1F3 Sector Number Sector Number
0 1 1 0 0 1F4 Cylinder Low Cylinder Low
0 1 1 0 1 1F5 Cylinder High Cylinder High
0 1 1 1 0 1F6 SDH Register SDH Register
0 1 1 1 1 1F7 Status Register Command Register
1 0 1 1 0 3F6 Alternate Status Digital Output
1 0 1 1 1 3F7 Drive Address Not Used
The above addresses are those used in the PC/AT. Of course
they are dependent on the decoding of the chip-select
signals. The registers accessed via /CS1 might differ
depending on the manufacturer of the drive. As far as I
know, they don't always follow the compatibility principle
with the first hard disk controller of the PC/AT.
The registers being accessed with /CS0 are also called the
"Task File", so sometimes the IDE is also referenced to as
"Task File Interface".
The error register can only be read. It contains valid
information only if the error bit in the status register is
set. Only five of the eight bits are used. They have the
Bit 7: Bad block. This bit is set when the requested
sector's ID contained a bad block mark (can be set
when formatting the disk).
Bit 6: Uncorrectable data error. Set when the sector
data can't be recreated (even with ECC).
Bit 4: Requested sector ID not found (wrong sector
Bit 2: Command was aborted due to drive status error or
Bit 1: Track 0 has not been found when recalibrating.
The unused bits are always read as zero. However, I guess
it's best not to rely on that!
The write precompensation register was previously used to
set the starting cylinder for write precompensation (a
slight shift of the serial data stream pulses to compensate
for some magnetic effects on the disk surface). Since IDE
drives handle all that internally, this function is not
needed any more. Today, this register is often used as a
parameter register for enabling or disabling look-ahead
reading. We'll have a deeper look at that when talking
about the various commands of IDE drives.
The sector-count register defines the number of sectors to
be read or written with the next read/write command. A zero
value causes 256 sectors to be processed, so the count
varies from 1 to 256. This register is also used during
drive initialization to specify the number of sectors per
track (remember the emulation capability).
The sector-number register contains the starting sector
number for any disk access. After a sector is processed,
and after the command is completed, this register is
updated. When an error occurs, this register contains the
ID number of the erroneous sector. Normally, the sector
numbers start with 1 and increase with each sector.
However, by reformatting the disk, this order and the values
may be changed.
The cylinder-low and cylinder-high registers contain the
10-bit cylinder number to be accessed. Since many drives
have more than 1024 cylinders today, the cylinder-high
register is often expanded to more than two bits. Like the
sector-number register, these registers are updated after
command completion and after errors. They are also used
during drive initialization as the number-of-cylinders
The SDH register is a special register serving several
functions. SDH is an abbreviation for "Sector size, Drive
and Head". The bits of this register are arranged as
Bit 7: Historical: Extension Bit. When zero, CRC data is
appended to the sector's data fields. When set to
one, no CRC data is appended. Since today's
drives always use ECC error correction, this bit
must always be set (no CRC).
Bit 6-5: Sector Size. Since today's drives always have 512-
byte sectors (unchangeable by the user) because
PCs are not able to support other sizes, these
bits must always be 0-1.
Bit 4: Drive. This bit distinguishes between the two
connected drives when using the master-slave
chain. Single drives are always accessed with the
drive bit set to zero.
Bit 3-0: Head number. These four bits contain the head
number (that is, the disk surface number) for all
following accesses. Similar to the cylinder and
sector number, these bits are updated by the
drive. The head number field is also used for
drive initialization to specify the number of
The read-only status register contains eight single-bit
flags. It is updated at the completion of each command. If
the busy bit is active, no other bits are valid. The index
bit is valid independent of the applied command. The bit
Bit 7: Busy flag. When this flag is set, the task file
registers must not be accessed due to internal
Bit 6: Drive ready. This bit is set when the drive is up
to speed and ready to accept a command. When
there is an error, this bit is not updated until
the next read of the status register, so it can be
used to determine the cause of the error.
Bit 5: Drive write fault. Similar to "drive ready", this
bit is not updated after an error.
Bit 4: Drive seek complete. This bit is set when the
actuator of the drive's head is on track. This
bit also is updated similarly to "drive ready".
Bit 3: Data request. This bit indicates that the drive
is ready for a data transfer.
Bit 2: Corrected data flag. Set when there was a
correctable data error and the data has been
Bit 1: Index. This bit is active once per disk
revolution. May be used to determine rotational
Bit 0: Error flag. This bit is set whenever an error
occurs. The other bits in the status register and
the bits in the error register will then contain
further information about the cause of the error.
The command register is used to pass commands to the drive.
There are many commands, not always using all parameters in
the task file. Command execution begins immediately after
the command is written to this register. Since this article
is already quite long, I will cover the commands, their
parameters, and their usage in another article, probably in
the next TCJ issue.
The alternate status register contains the same information
as the status register in the task file. The only
difference is that reading this register does not imply
interrupt acknowledge to reset a pending interrupt (as the
main status register does).
The digital output register contains only two valid data
bits. Bit 2 is the software reset bit, which causes a drive
reset when being set, and bit 1 is the interrupt enable
The drive-address register simply loops back the drive
select bit and head select bits of the currently selected
drive. This information normally is of no use for the
programmer or user.
Now that we had a look at the IDE interface, we also see the
physical limits of this interface definition. With a fully
expanded cylinder-high register, we are able to address up
to 65536 cylinders, with up to 16 heads and up to 256
sectors per track. This results in a maximum addressable
drive capacity of 128 gigabytes. I think this should be
enough for microcomputing!! However, even if the PC/AT BIOS
limitations are encountered, we could address 1024 cylinders
with 16 heads and 64 sectors per tracks, giving 512
megabytes maximum capacity. This is also not bad, at least
for small (8-bit) computer systems, where complete
application software packages require only about 100
kilobytes of disk space.
Next time I would like to talk about the applicable commands
of IDE drives and give examples of how to write software
that accesses those drives.
List of Abbreviations:
AT Advanced Technology Class of PC's
BIOS Basic I/O System Hardware-dependent part of OS
CMOS Complementary Metal-Oxid-Silicon Semiconductor technology
CRC Cyclic Redundancy Check Error detection code, see also ECC
ECB ??? European standard 8-bit system bus
ECC Error Correction Code Additional data for security
IDE Integrated Drive Electronics Intelligent hard disk interface
IEEE Institute of Electrical and Electronics Engineers
I/O Input/Output (self-explanatory)
ISA Industry Standard Architecture PC/AT expansion bus
LED Light Emmitting Diode Optoelectronical component
OS Operating System Software which makes computers usable
PC Personal Computer Synonym for the worst computer architecture
TTL Transistor-Transistor-Logic Digital component standard (74xx series)
XT eXtended Technology Class of PCs, previous to AT
ZBR Zone Bit Recording Variable Density Recording Method
Connecting IDE Drives, Part II
In Part I (printed in the previous issue of TCJ) we covered the
basics of the IDE interface in terms of history, concept,
hardware, and register structure. This time we want to dig deeper
into the software side of those drives.
Using common terminology, I often simply refer to the "drive"
when, in fact, I am thinking of the integrated controller of an
IDE drive. However, when explicitly talking of an external
controller like the WD1010, I always refer to the "controller".
Let us first recall the Task File. It consists of the data
register, a set of six parameter registers, and the
command/status register. For those who don't have Part II lying
nearby, here is a shortform:
Relative Address Register Abbr.
0 Data Register D
1 Error Reg. / Write Precomp. Reg. E / WP
2 Sector Count SC
3 Sector Number SN
4 Cylinder Low C
5 Cylinder High C
6 SDH (Sector Size, Drive, Head) D,H
7 Status Reg. / Command Reg.
Also remember that the data register is the only 16-bit register!
Every parameter register of the task file is freely accessible as
long as there is no active command. Before loading the command
register, all related parameter registers must contain the
appropriate values. They may be loaded in any order. After the
command register is loaded, the issued command is immediately
started. The original WD1010 hard disk controller chip had a flag
(bit 1 of the status register) which was set during execution.
With IDE drives, the BUSY flag of the status register is simply
set until the command execution is completed.
The WD1010 controller chip knew only 6 commands. However, some of
the commands have option flags within them. To support additional
features, today's drives have many more commands. The following
is a list of common commands, options, and needed parameters,
with the WD1010 commands marked by an asterisk and the
manufacturer-dependent expansions marked with a plus sign:
Command Type 7 6 5 4 3 2 1 0 Hex Parameters
Recalibrate * 0 0 0 1 (Rate) 10-1F D
Read Sector * 0 0 1 0 0 M L T 20-27 SC,SN,C,D,H
Write Sector * 0 0 1 1 0 M L T 30-37 SC,SN,C,D,H
Scan ID / Verify * 0 1 0 0 0 0 0 T 40,41 D,(SC,SN,C,H)