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Gates and Flip-Flops Abstract


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Gates and Flip-Flops
Abstract:
This experiment aims to investigate the operation of various logic gates and to construct some counting circuits. The similarities between Boolean Algebras and logical operations in electronics will be observed. Various truth tables for the logical operations will be made. The operation of a flip-flop – a circuit with memory – will be investigated and this will be applied in an integrated circuit which can count.
Basic Theory:
A Boolean algebra is a set B together with two operations, and , such that the following axioms hold:


  1. Commutativity:

  2. Associativity:

  3. Distributivity:

  4. Existence of a zero: such that

  5. Existence of a unity: such that

  6. Existence of complements: such that

We can combine these operations, using the above axioms, to get other operations, such as “exclusive or”: . The set B can be thought of as the set of all propositions. This enables us to formalize our ideas about statements. We are then justified in calling the operations on a Boolean algebra “logical operations”.


A truth table is a means of verifying a relation between two propositions. For example, we can verify the relation that “proposition P holds whenever P holds” (tautology) as follows:


P



P

0

1

0

0

0

1

1

0

0

1

1

1

A logic gate is an electronic device which can perform logical operations. The input is a voltage – either a non-zero voltage or a zero voltage. Similarly, the output is either a zero voltage or a non-zero voltage. These are the so-called “logical states”. We think of the non-zero voltage as a 1 and of the zero voltage as a 0. Thus in thinking about logic gates we ought to consider the Boolean algebra B = {0,1}. Just as in a Boolean algebra, the basic operations with which we concern ourselves are (AND), (OR) and C (NOT). Other operations can be obtained by composing these three basic operations.


A flip-flop is an electronic device with memory. A simple flip-flop circuit is the following:
(insert Figure 1)
The gates are NAND gates. If A and B are 1 and X is 1, then both inputs of G2 are high, so Y is 0. But the circuit is symmetric: if A and B are high and Y is 1, then X is 0. Thus, for A and B being 1, two logical states are equally possible. The flip-flop therefore has two stable states. Which state it is in depends on past history. To configure the memory, make A zero. This produces the state where X is 1 and Y is zero.
Procedure and Results:
1. AND and Not Gates:
Integrated circuit (I.C.) SN7410 was used to investigate the NAND. This I.C. takes three arguments as the input. Thus, in this NAND operation, inputs a, b and c combine as , so the effect is to negate the output of the AND operation. The following truth table was obtained:


Input a

Input b

Input c

Output

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

0

This I.C. can also take two arguments as the input. To see this, one simply disconnects one of the input voltages and obtains a truth table:




Input a

Input b

Output

0

0

1

0

1

1

1

1

0

The I.C. can be made into an AND gate by complementing the output. Thus if arguments a, b and c are the input, they combine as. In practical terms, this means connecting the output to a NOT gate. The following truth table was obtained for the AND gate:




Input a

Input b

Input c

Output

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

Furthermore, we can inhibit one of the inputs – c, say, by putting it through a NOT gate before putting it through the AND gate. Thus, arguments a, b and c combine as . The following truth table was obtained:




Input a

Input b

Input c

Output

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

0

Finally, inputs a and b were connected to the clock, and a pulsed output was observed for input c set to zero.




  1. Or and Nor Gates:

An OR gate was constructed from the NAND gate as in figure 2.


(Insert Figure 2)
Now arguments a and b combine as . The action of the OR gate was verified by tabulating the following truth table:


Input a

Input b

Output

0

0

0

0

1

1

1

0

1

1

1

1

The output of the OR gate was complemented in order to make a NOR gate. Now arguments a and b combine as . The following truth table was obtained:




Input a

Input b

Output

0

0

1

0

1

0

1

0

0

1

1

0




  1. Exclusive OR and Exclusive NOR Gates:

The exclusive OR gate gives an output of 1 whenever either input a or input b is 1, but not when both a and b are 1. This composite operation can be made out of NAND gates in three ways, shown in figure 3.


(Insert Figure 3)
The truth table was obtained for each case. These were identical, and so there is need only to include one of them:


Input a

Input b

Output

0

0

0

0

1

1

1

0

1

1

1

0

The exclusive NOR gate was made by connecting the output of the exclusive OR gate to a NOT gate. The following truth table was obtained:




Input a

Input b

Output

0

0

1

0

1

0

1

0

0

1

1

1



  1. The Flip-Flop:

(Insert Figures 4 and 5)


The flip-flop used is the J – K master-slave flip-flop circuit shown in figure 4. In fact, the I.C. 7476N can be used instead of this circuit (figure 5). This circuit takes two arguments, J and K, although there are in fact five inputs into the circuit: J, K, Ck, Cr and Pr. There are two outputs, called Q and QC, and as the notation indicates, they are complementary. The state of the flip-flop is given by Q and QC and this depends on the inputs J and K. It can be changed by pulses on the clock (Ck).
The outputs Q and QC depend on J and K respectively. Thus, if J = 1 and K = 0, then Q = 1 and QC = 0. However, if we change J to 0 and K to 1, there is no change in Q and QC until a pulse occurs at the clock input. Thereafter the states of Q and QC flip.
The action of the Flip-Flop can be understood by using the following table:
Let the initial state be determined by J = 1 and K = 0.


J

K

Q

QC

0

0







0

1






1

0







1

1






Thus, if we let J = 0 and K = 1, we find that no chage in Q and QC takes place. On the other hand, if we let J = 0 and K = 1, then Q becomes 0 and QC becomes 1. Similarly, if we let J = 1 and K = 0, then Q becomes 1 and QC becomes 0 (i.e. there is no change). Finally, if we let J and K be 1, then there are two possible outputs: Q = 1 and QC = 0, or Q = 0 and QC = 1. The outputs change as each clock pulse arrives.




  1. Counters

The circuit of figure 6 was set up. This circuit has four outputs (the LED’s) and there are 16 (24) combinations of on or off. Thus, the circuit can count to 16 in base 2 (binary). This is accomplished by the circuit producing different outputs in the following sequential way:


0000

0001


0010

0011


0100

0101


0110

0111


1000

1001


1010

1011


1100

1101


1110

1111
Adding the dashed circuit makes the circuit finish counting after ten steps, and so the circuit then counts to ten.


The circuit of figure 7 was then set up. This is the synchronous scale of 16. It is synchronous because the clock provides a common pulse to each flip-flop and so all action takes place just after each clocking pulse, and this action depends on the configuration of the system just before each clock pulse. This compares to the previous circuit – a ripple circuit – where each stage is “clocked” by the output of the previous stage. This can give rise to undesirable transient effects.
(Insert figure 7).
Conclusion:
The logical operations performed by the various gates were verified and the Flip-Flop circuit was used to make a counting scale.


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