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Ece8223 Exercise es-5: Source-coupled pair version 6

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ECE8223 Exercise ES-5: Source-coupled pair version 1.6

ES-5 One of the workhorse subcircuits of analog IC design is the of the Source-Coupled Pair (SCP), as represented by figure ES-5.1

Figure ES-5.1. nMOS source-coupled pair (SCP) topologies
The small-signal transfer characteristics of an amplifier are
(1) transfer gain AVO = vO/vI

(2) input resistance Rin = vI/iI and

(3) output resistance Rout= vO/iO.
For MOS devices since the input is to a V(gate) capacitance. For the passive-load topologies Rout = Rdx and
And for the active load topologies


for which and for the level-1 analyses and we might expect them to be mildly inadequate. As a mild analytical upgrade, the values of gm and gDS were be modified in exercises ES-2 to first-order curvefit forms:


For this circuit you should sweep V3 from –0.5V to 0.5V and step the current setting Ix through a reasonable range, such as 25uA to 300uA, step 5uA. This should result in a family of curves for transfer gain. (Figure ES-4.2a). A “performance analysis” plot of the Max(dVo1/dVin) and Max(dV02/dVin) are illustrated by figure EC-5-2

Figure ES-5.2a Transfer gain, SCP Figure ES-5.2b Excel Comparisons:

pSPICE dVo/dVin vs analytical dVo/dVin

The analytical Excel/pSPICE comparisons make use of formulae (ES-5.1) and (ES-5.2)
Now import your pSPICE data for dVo/dVin vs Ix (figure ES-4.2b) into the (Excel) spreadsheet and compare to the analytical results of using equations (ES-5.1) and (ES-5-2). If the fit parameters for gm and gDS were reasonablywell adjusted then the comparisons should be fairly close, as represented by figure ES-5.2b..


  1. Using this discussion as a template, repeat this analysis but for MOSIS process VO1V. You should have three figures, which you should label as your figures ES-5.1, ES-5.2a, ES-5.2b. The template indicates all of the necessary constructs. The execution does rely on you having accomplished an expertise with the pSPICE and Excel utilities through the previous exercises.

  1. Repeat part (a) but for the circuit of figure ES-5.4 (inverted version of figure ES-5.1). Change figure numbers appropriately.

Figure ES-5.4: SCP with pMOS drivers and nMOS active load

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